Multi-chip modules and packages in which two or more microelectronic components are positioned on a single substrate, typically require wiring or other connection between the chips for conveying data, control signals, addresses and the like. "Microelectronic components" include integrated circuits, chip capacitors, chip resistors and crystals or oscillators. Typically, each substrate will include a plurality of locations, for forming such connections, generally referred to as pins or pads. In previous devices, interconnection was achieved between the chips using one or more layers of metalization which include a plurality of metallic lines or traces on the substrate leading, in the desired fashion, from a pad connected to one chip to a pad connected to another chip (typically by wires soldered or otherwise bonded to the pads). These previous devices were difficult to fabricate particularly in cases in which the topology of the desired connection between the chips required a crossing-over of the electrical connections. As depicted in FIG. 1, a crossing-over is required for the connection 30 between pad 118c and pad 116b and the connection 34 between pad 118a and pad 116c. The configuration shown in FIG. 1 has been simplified , for clarity, compared to the numerous pads and connections often needed in a multi-chip module or package. In the configuration as depicted in FIG. 1, first and second chips 112, 114, or dies, include a plurality of pads 116a-116n, 118a-118n. A plurality of metalization traces 22-44 are formed on or in the substrate 8 terminating in metalization connection pads 46a-46cc. The chip pads 116a-116n, 118a-118n are connected to the metalization termination pads 46 by means such as wire bonds 46a-48cc, tape bonds and the like.
In order to avoid electrical contact between the traces 30 and 34, despite the crossing-over thereof, previous devices typically required use of at least two layers of metalization 50a, 50b. In FIG. 1, the location of traces in the second layer 50b is indicated by phantom lines. Connection between the layers was provided by vertical conductive structures known as vias 52, as depicted, for example in FIG. 2. FIG. 1 depicts numerous other cross-overs achieved using traces having portions 24', 26', 36', 40', 42'44' located in the second metalization layer 50b. Trace 40, for example, has one portion in the first layer 50a to cross-over trace 38' another portion 40' in the second layer 50b to cross-over trace 42 and another portion in the first layer 50a to cross-over trace 44'.
Although this connection method is capable of providing the desired interconnection between the chips, forming vias 50 (FIG. 2) and forming more than one metalization layer 50b adds to the expense of the final product and adds to the number of process steps needed to form the product, thus increasing processing cost.
Accordingly, it would be advantageous to provide for interconnection between chips in a multi-chip module or package, allowing for crossing-over connections while avoiding the need for multiple layers of metalization or formation of vias.